SY89871U buffer equivalent, 2.5ghz any diff. in-to-lvpecl programmable clock divider/fanout buffer.
Precision Edge®
* Two matched-delay outputs: - Bank A: undivided pass-through (QA) - Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
* Matched delay: all .
The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0.
The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider .
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